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L4972A
2A SWITCHING REGULATOR
1

Features
2A OUTPUT CURRENT 5.1V TO 40V OUTPUT VOLTAGE RANGE 0 TO 90% DUTY CYCLE RANGE INTERNAL FEED-FORWARD LINE REG. INTERNAL CURRENT LIMITING PRECISE 5.1V 2% ON CHIP REFERENCE RESET AND POWER FAIL FUNCTIONS INPUT/OUTPUT SYNC PIN UNDER VOLTAGE LOCK OUT WITH HYSTERETIC TURN-ON PWM LATCH FOR SINGLE PULSE PER PERIOD VERY HIGH EFFICIENCY SWITCHING FREQUENCY UP TO 200KHz THERMAL SHUTDOWN CONTINUOUS MODE OPERATION
Figure 1. Packages
PowerDIP20 (16+2+2)
SO20
Table 1. Order Codes
Part Number L4972A L4972AD L4972AD013TR Package DIP20 (16+2+20) SO20 SO20 in Tape & Reel

2
Description
The L4972A is a stepdown monolithic power switching regulator delivering 2A at a voltage variable from 5.1 to 40V. Realized with BCD mixed technology, the device Figure 2. Block Diagram
uses a DMOS output transistor to obtain very high efficiency and very fast switching times. Features of the L4972 include reset and power fail for microprocessors, feed forward line regulation, soft start, limiting current and thermal protection. The device is mounted in a Powerdip 16 + 2 + 2 and SO20 large plastic packages and requires few external components. Efficient operation at switching frequencies up to 200KHz allows reduction in the size and cost of external filter component.
May 2005
Rev. 3 1/22
L4972A
Table 2. Pin Description
N 1 2 3 4 Pin BOOTSTRAP RESET DELAY RESET OUT RESET INPUT Function A Cboot capacitor connected between this terminal and the output allows to drive properly the internal D-MOS transistor. A Cd capacitor connected between this terminal and ground determines the reset signal delay time. Open Collector Reset/power Failand the output voltages are safe. Signal Output. This output is high when the supply Input of Power Fail Circuit. The threshold is 5.1V. It may be connected via a divider to the input for power fail function. It must be connected to the pin 14 an external 30K resistor when power fail signal not required. Common Ground Terminal A series RC network connected between this terminal and ground determines the regulation loop gain characteristics. Soft Start Time Constant. A capacitor is connected between the sterminal and ground to define the soft start time constant. The Feedback Terminal of the Regulation Loop. The output is connected directly to this terminal for 5.1V operation; It is connected via a divider for higher voltages. Multiple L4972A's are synchronized by connecting pin 10 inputs together or via an external syncr. pulse. Unregulated Input Voltage. Not Connected. 5.1V Vref Device Reference Voltage. Internal Start-up Circuit to Drive the Power Stage. Rosc. External resistor connected to ground determines the constant charging current of Cosc. Cosc. External capacitor connected to ground determines (with Rosc) the switching frequency. Regulator Output.
5, 6 15, 16 7 8 9 10 11 12, 19 13 14 17 18 20
GROUND FREQUENCY COMPENSATION SOFT START FEEDBACK INPUT SYNC INPUT SUPPLY VOLTAGE N.C. Vref Vstart OSCILLATOR OSCILLATOR OUTPUT
Figure 3. Pin Connection (Top view)
BOOTSTRAP RESET DELAY RESET OUT P. FAIL INPUT GND GND FREQ. COMP. SOFT START FEEDBACK IN. SYNC INPUT
1 2 3 4 5 6 7 8 9 10
DIP20
20 19 18 17 16 15 14 13 12 11
OUTPUT N.C. C OSC R OSC GND GND Vstart Vref N.C. Vi
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Table 3. Absolute Maximum Ratings
Symbol V11 V11 V20 I20 VI V4, V8 V3 I3 V2, V7, V9, V10 I2 I7 I8 Ptot TJ, Tstg
(*) SO-20
Parameter Input Voltage Input Operating Voltage Output DC Voltage Output Peak Voltage at t = 0.1s f = 200kHz Maximum Output Current Boostrap Voltage Boostrap Operating Voltage Input Voltage at Pins 4, 12 Reset Output Voltage Reset Output Sink Current Input Voltage at Pin 2, 7, 9, 10 Reset Delay Sink Current Error Amplifier Output Sink Current Soft Start Sink Current Total Power Dissipation at TPINS 90C at Tamb = 70C (No copper area on PCB) Junction and Storage Temperature
Value 55 50 -1 -5 Internally Limited 65 V11 + 15 12 50 50 7 30 1 30 5 / 3.75(*) 1.3/1 (*) -40 to 150
Unit V V V V V V V V mA V mA A mA W W C
Table 4. Thermal Data
Symbol Rth j-pins Rth j-amb Parameter Thermal Resistance Junction-Pins Thermal Resistance Junction-ambient max, max, PowerDIP 12 60 SO20 16 80 Unit C/W C/W
3
Circuit Operation
The L4972A is a 2A monolithic stepdown switching regulator working in continuous mode realized in the new BCD Technology. This technology allows the integration of isolated vertical DMOS power transistors plus mixed CMOS/Bipolar transistors. The device can deliver 2A at an output voltage adjustable from 5.1V to 40V and contains diagnostic and control functions that make it particularly suitable for microprocessor based systems. 3.1 BLOCK DIAGRAM The block diagram shows the DMOS power transistors and the PWM control loop. Integrated functions include a reference voltage trimmed to 5.1V 2%, soft start, undervoltage lockout, oscillator with feedforward control, pulse by pulse current limit, thermal shutdown and finally the reset and power fail circuit. The reset and power fail circuit provides an output signal for a microprocessor indicating the status of the system. Device turn on is around 11V with a typical 1V hysterysis, this threshold porvides a correct voltage for the driving stage of the DMOS gate and the hysterysis prevents instabilities. An external bootstrap capacitor charge to 12V by an internal voltage reference is needed to provide correct gate drive to the power DMOS. The driving circuit is able to source and sink peak currents of around 0.5A to the gate of the DMOS transistor. A typical switching time of the current in the DMOS transistor is 50ns. Due to the fast commutation switching frequencies up to 200kHz are possible. The PWM control loop consists of a sawtooth oscillator, error amplifier, comparator, latch and the output
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L4972A
stage. An error signal is produced by comparing the output voltage with the precise 5.1V 2% on chip reference. This error signal is then compared with the sawtooth oscillator in order to generate frixed frequency pulse width modulated drive for the output stage. A PWM latch is included to eliminate multiple pulsing within a period even in noisy environments. The gain and stability of the loop can be adjusted by an external RC network connected to the output of the error amplifier. A voltage feedforward control has been added to the oscillator, this maintains superior line regulation over a wide input voltage range. Closing the loop directly gives an output vol-tage of 5.1V, higher voltages are obtained by inserting a voltage divider. At turn on, output overcurrents are prevented by the soft start function (fig. 5). The error amplifier is initially clamped by an external capacitor, Css, and allowed to rise linearly under the charge of an internal constant current source. Output overload protection is provided by a current limit circuit. The load current is sensed by a internal metal resistor connected to a comparator. When the load current exceeds a preset threshold, the output of the comparator sets a flip flop which turns off the power DMOS. The next clock pulse, from an internal 40kHz oscillator, will reset the flip flop and the power DMOS will again conduct. This current protection method, ensures a constant current output when the system is overloaded or short circuited and limits the switching frequency, in this condition, to 40kHz. The Reset and Power fail diagram (fig. 7), generates an output signal when the supply voltage exceeds a threshold programmed by an external voltage divider. The reset signal, is generated with a delay time programmed by a external capacitor on the delay pin. When the supply voltage falls below the threshold or the output voltage goes below 5V, the reset output goes low immediately. The reset output is an open drain. Fig. 7A shows the case when the supply voltage is higher than the threshold, but the output voltage is not yet 5V. Fig. 7B shows the case when the output is 5.1V, but the supply voltage is not yet higher than the fixed threshold. The thermal protection disables circuit operation when the junction temperature reaches about 150C and has a hysterysis to prevent unstable conditions. Figure 4. Feedforward Waveform.
Figure 5. Soft Start Function.
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L4972A
Figure 6. Limiting Current Function.
Figure 7. Reset and Power Fail Functions
A
B
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4
Electrical Characteristcs
Table 5. Electrical Characteristcs Refer to the test circuit, TJ = 25C, Vi = 35V, R4 = 30K, C9 = 2.7nF, fSW = 100KHz typ, unless otherwise specified.
Symbol Vi Vo Parameter Input Volt. Range (pin 11) Output Voltage Line Regulation Load Regulation Dropout Voltage between Pin 11 and 20 Max Limiting Current Efficiency (*) Test Condition Vo = Vref to 40V Io = 2A (**) Vi =15V to 50V Io= 1A; Vo = Vref Vi =15V to 50V Io = 0.5A; Vo= Vref Vo = Vref Io= 0.5A to 2A Io = 2A Vi = 15V to 50V Vo= Vref to 40V Io = 2A, f = 100KHz Vo = Vref Vo = 12V 2.5 Min. 15 5 5.1 12 7 0.25 2.8 Typ. Max. 50 5.2 30 20 0.4 3.5 Unit V V mV mV V A Fig. 8 8 DYNAMIC CHARACTERISTICS
Vo Vo
Vd I20L
75 56 90
85 90 60 100 2 1 110 6
% % dB KHz % % KHz 8 8 8 8 8
SVR f
Supply Voltage Ripple Rejection Vi = 2VRMS; Io= 1A f = 100Hz; Vo= Vref Switching Frequency Voltage Stability of Switching Frequency Temperature Stability of Switching Frequency Maximum Operating Switching Frequency Vi = 15V to 45V Tj = 0 to 125C Vo= Vref R4 = 15K Io = 2A C9= 2.2nF
f/Vi
f/Tj fmax
200
(*) Only for DIP version (**) Pulse testing with a low duty cycle
Vref SECTION (pin 13) V13 V13 V13 Reference Voltage Line Regulation Load Regulation Vi = 15V to 50V I13 = 0 to 1mA Tj = 0C to 125C V13 = 0 11.4 Vi = 15 to 50V I14 = 0 to 1mA V15 = 0V 10 V8 = 0; S1 = D V8 = 0; S1 = B; S2 = B 5 5.1 10 20 0.4 70 12 0.6 50 80 11 1 13 16 19 23 12 12.6 1.4 200 5.2 25 40 V mV mV mV/C mA V V mV mA V V mA mA 10 10 10 10 10 10 10 10 10 12 12 12 12
V13 /T Average Temperature Coefficient Reference Voltage I13 short V14 V14 V14 I14 short V11on I11Q I11OQ Short Circuit Current Limit Reference Voltage Line Regulation Load Regulation Short Circuit Current Limit Turn-on Threshold Quiescent Current Operating Supply Current VSTART SECTION (pin 15)
DC CHARACTERISTICS V11 Hyst Turn-off Hysteresys
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Table 5. Electrical Characteristcs (continued) Refer to the test circuit, TJ = 25C, Vi = 35V, R4 = 30K, C9 = 2.7nF, fSW = 100KHz typ, unless otherwise specified.
Symbol I20L I8 V8 Parameter Out Leak Current Soft Start Source Current Output Saturation Voltage Test Condition Vi = 55V; S3 = A; V8= 0 V8 = 3V; V9= 0V I8 = 20mA; V11= 10V I8= 200A; V11= 10V I7 = 100A; S1 = C; V9 = 4.7V I7 = 100A; S1 = C; V9= 5.3V V7 = 1V; V7 = 4.7V V7 = 6V; V9 = 5.3V S1 = B; RS = 10K S1 = A; RS= 10 15 < Vi < 50V RS= 50 S1 = A S1 = B; S2 = B S1 = B; S2 = B Vi = 15V Vi = 45V S1 = A; I17= 100A S1 = A; I17= 1mA Vi = 15V to 50V; V8 = 0; S1 = B; S2 = B; S4 = B V8 = 0; S1 = B; S2 = B; S4 = B V10= V18= 0.9V; S4 = B; S1 = B; S2 = B V10= 2.5V 4 Vthr = 2.5V 0.3 Vref -130 4.77 4.95 1 30 10 0.4 100 5 0.5 Vref -100 Vref -200 5.1 1.1 60 0.8 Vref -80 Vref -160 5.25 1.2 80 2.4 -0.3 2.5 1.2 60 60 80 2 1.5 2.5 5.5 270 2.7 0.9 5.5 0.4 1.5 300 10 100 100 150 150 0.4 3 6 1.2 80 115 Min. Typ. Max. 2 150 1 0.7 Unit mA A V V V V A A A dB dB mV V V V A mA V V mA mA V s V mV V mV V V A mA V A Fig. 12 13 13 13 14 14 14 14 14 14 14 14 12 12 12 12 12 12 12 12 12 - - 15 15 15 15 15 15 15 15 7/22
SOFT START (pin 8)
ERROR AMPLIFIER V7H V7L I7H -I7L I9 GV SVR VOS V18 V18 High Level Out Voltage Low Level Out Voltage Source Output Current Sink Output Current Input Bias Current DC Open Loop Gain Supply Voltage Rejection Input Offset Voltage Ramp Valley Ramp Peak
RAMP GENERATOR (pin 18)
I18 I18 V10 V10 I10L I10H V10
Min. Ramp Current Max. Ramp Current Low Input Voltage High Input voltage Sync Input Current with Low Input Voltage Input Current with High Input Voltage Output Amplitude Output Pulse Width
SYNC FUNCTION (pin 10)
tW
V9R V9F V2H V2L I2SO I2SI V3S I3
RESET AND POWER FAIL FUNCTIONS Rising Thereshold Voltage (pin 9) Vi = 15 to 50V V4 = 5.3V Falling Thereshold Voltage (pin 9) Vi = 15 to 50V V4 = 5.3V Delay High Threshold Volt. Delay Low Threshold Volt. Delay Source Current Delay Source Sink Current Output Saturation Voltage Output Leak Current Vi = 15 to 50V V4 = 5.3V; V9 = V13 Vi = 15 to 50V;V4 = 4.7V; V9 = V13 V4 = 5.3V; V2 = 3V V4 = 4.7V; V2 = 3V I3 = 15mA; S1 = B V4 = 4.7V V3 = 50V; S1 = A
L4972A
Table 5. Electrical Characteristcs (continued) Refer to the test circuit, TJ = 25C, Vi = 35V, R4 = 30K, C9 = 2.7nF, fSW = 100KHz typ, unless otherwise specified.
Symbol V4R V4H I4 Parameter Rising Threshold Voltage Hysteresis Input Bias Current Test Condition V9 = V13 Min. 4.95 0.4 Typ. 5.1 0.5 1 Max. 5.25 0.6 3 Unit V V A Fig. 15 15 15
Figure 8.
TYPICAL PERFORMANCES (using evaluation board) : n = 83% (Vi = 35V ; Vo = VREF ; Io = 2A ; fsw = 100KHz) Vo RIPPLE = 30mV (at 1A) Line regulation = 12mV (Vi = 15 to 50V) Load regulation = 7mV (Io = 0.5 to 2A) for component values Refer to the fig. 8 (Part list). Figure 9. Component Layout of fig. 8. Evaluation Board Available (only for DIP version)
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L4972A
PART LIST R1 = 30K R2 = 10K R3 = 15K R4 = 30K R5 = 22 R6 = 4.7K R7 = see table 6 R8 = OPTION R9 = 4.7K * C1 = C2 = 1000mF 63V EYF (ROE) C3 = C4 = C5 = C6 = 2,2F 50V C7 = 390pF Film C8 = 22nF MKT 1837 (ERO) C9 = 2.7nF KP 1830 (ERO) C10 = 0.33F Film C11 = 1nF ** C12 = C13 = C14 = 100F 40V EKR (ROE) C15 = 1F Film D1 = STPS5L60 L1 = 150H core 58310 MAGNETICS 45 TURNS 0.91mm (AWG 19) COGEMA 949181
* 2 capacitors in parallel to increase input RMS current capability. * * 3 capacitors in parallel to reduce total output ESR.
Table 6. V0
12V 15V 18V 24V
Note: In the Test and Application Circuit for L4972D are not mounted C2, C14 and R8.
R9
4.7k 4.7k 4.7k 4.7k
R7
6.2k 9.1k 12 18
Table 7. Suggested Boostrap Capacitors
Operating Frequency f = 20KHz f = 50KHz f = 100KHz f = 200KHz f = 500KHz Boostrap Cap.c10 680nF 470nF 330nF 220nF 100nF
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L4972A
Figure 10. P.C. Board and Component Layout of the Circuit of Fig. 8.
Figure 11. DC Test Circuits
Figure 12.
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L4972A
Figure 13.
Figure 14.
Figure 15.
Figure 16. Quiescent Drain Current vs. Supply Voltage (0% duty cycle - see fig. 12).
Figure 17. Quiescent Drain Current vs. Junction Temperature (0% duty cycle).
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L4972A
Figure 18. Quiescent Drain Current vs. Duty Cycle. Figure 21. Reference Voltage (pin 14) vs. Vi (see fig. 11).
Figure 19. Reference Voltage (pin 13) vs. Vi (see fig. 11).
Figure 22. Reference Voltage (pin 14) vs. Junction Temperature (see fig. 11).
Figure 20. Reference Voltage (pin 13) vs. Junction Temperature (see fig. 11).
Figure 23. : Ref. Voltage 5.1V (pin 13) Supply Voltage Ripple Rejection vs. Frequency
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L4972A
Figure 24. Switching Frequency vs. Input Voltage (see fig. 8). Figure 27. Maximum Duty Cycle vs. Frequency.
Figure 25. Switching Frequency vs. Junction Temperature (see fig. 8).
Figure 28. Supply Voltage Ripple Rejection vs. Frequency (see fig. 8).
Figure 26. Switching Frequency vs. R4 (see fig.8).
Figure 29. Efficiency vs. Output Voltage.
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L4972A
Figure 30. Line Transient Response (see fig. 8). Figure 33. .Dropout Voltage between Pin 11 and Pin 20 vs. Junction Temperature.
Figure 31. Line Transient Response (see fig. 8).
Figure 34. Power Dissipation (device only) vs. Input Voltage.
Figure 32. Dropout Voltage between Pin 11 and Pin 20 vs. Current at Pin 20.
Figure 35. Power Dissipation (device only) vs. Input Voltage.
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L4972A
Figure 36. Power Dissipation (device only) vs. Output Voltage. Figure 39. Power Dissipation (device only) vs. Output Current
Figure 37. Power Dissipation (device only) vs. Output Voltage
Figure 40. Efficiency vs. Output Current.
Figure 38. Power Dissipation (device only) vs. Output Current
Figure 41. Test PCB Thermal Characteristic.
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L4972A
Figure 42. Rth j-amb vs. Area on Board Heatsink (DIP 16+2+2) Figure 45. Maximum Allowable Power Dissipation vs. Ambient Temperature (SO20)
Figure 43. Rth j-amb vs. Area on Board Heatsink (SO20)
Figure 46. Open Loop Frequency and Phase of Error Amplifier (see fig. 14).
Figure 44. Maximum Allowable Power Dissipation vs. Tamb (Powerdip)
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L4972A
Figure 47. 2A - 5.1V Low Cost Application Circuit.
Figure 48. A 5.1V/12V Multiple Supply. Note the Synchronization between the L4972A and L4970A.
Figure 49. L4972A's Sync. Example.
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L4972A
Figure 50. 1A/24V Multiple Supply. Note the synchronization between the L4972A and L4962
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L4972A
5
Package Information
Figure 51. PowerDIP20 Mechanical Data & Package Dimensions
DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.38 0.51 0.85
mm TYP. MAX. MIN. 0.020 1.40 0.50 0.50 24.80 8.80 2.54 22.86 7.10 5.10 3.30 1.27 0.015 0.033
inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
0.055 0.020 0.020 0.976 0.346 0.100 0.900 0.280 0.201 0.130
Powerdip 20
0.050
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L4972A
Figure 52. SO20 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO20
0016022 D
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L4972A
6
Revision History
Table 8. Revision History
Date June 2000 May 2005 Revision 2 3 First Issue Modified look & feel layout. Changed the name of D1 in the Part list to page 9/22. Description of Changes
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L4972A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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